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2M x 32-Bit Dynamic RAM Module
HYM 322030S/GS-60/-70
Advanced Information
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2 097 152 words by 32-bit organization Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) 70 ns access time 130 ns cycle time (-70 version) Fast page mode capability 40 ns cycle time (-60 version) 45 ns cycle time (-70 version) Single + 5 V ( 10 %) supply Low power dissipation max. 3300 mW active (-60 version) max. 3025 mW active (-70 version) CMOS - 22 mW standby TTL - 44 mW standby
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CAS-before-RAS refresh RAS-only-refresh Hidden-refresh 4 decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height Utilizes four 2M x 8 - DRAMs in 400 mil SOJ-packages 2048 refresh cycles / 32 ms Tin-Lead contact pads (S - version) Gold contact pads (GS - version)
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Ordering Information Type HYM 322030S-60 HYM 322030S-70 HYM 322030GS-60 HYM 322030GS-70 Ordering Code Q67100-Q976 Q67100-Q977 Q67100-Q2018 Q67100-Q2019 Package L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 L-SIM-72-9 Description DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns)
Semiconductor Group
561
09.94
HYM 322030S/GS-60/-70 2M x 32-Bit
The HYM 322030S/GS-60/-70 is a 8 M Byte DRAM module organized as 2 097 152 words by 32-bit in a 72-pin single-in-line package comprising four HYB 5117800BSJ 2M x 8 DRAMs in 400 mil wide SOJ-packages mounted together with four 0.2 F ceramic decoupling capacitors on a PC board. Each HYB 5117800BSJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 322030S/GS-60/-70 dictates the use of early write cycles.
Pin Definitions and Functions Pin No. A0R-A10R A0C-A9C DQ0-DQ31 CAS0 - CAS3 RAS0, RAS2 WE Function Row Address Inputs Column Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
Presence Detect Pins -60 PD0 PD1 PD2 PD3 N.C. N.C. N.C. N.C. -70 N.C. N.C.
VSS
N.C.
Semiconductor Group
562
HYM 322030S/GS-60/-70 2M x 32-Bit
Pin Configuration (top view)
Semiconductor Group
563
HYM 322030S/GS-60/-70 2M x 32-Bit
Block Diagram
Semiconductor Group
564
HYM 322030S/GS-60/-70 2M x 32-Bit
Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 C Storage temperature range......................................................................................... - 55 to 125 C Soldering temperature ............................................................................................................ 260 C Soldering time ............................................................................................................................. 10 s Input/output voltage ........................................................................ - 0.5 V to min (VCC + 0.5, 7.0) V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation..................................................................................................................... 4.2 W Data out current (short circuit) ................................................................................................ 50 mA Note:Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics1) TA = 0 to 70 C, VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -60 version -70 version Standby VCC supply current (RAS = CAS = VIH) Average VCC supply current during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -60 version -70 version Symbol Limit Values min. max. 2.4 - 0.5 2.4 - - 10 - 10 Unit Test Condition
VIH VIL VOH VOL II(L) IO(L) ICC1
VCC + 0.5 V
0.8 - 0.4 10 10 V V V A A
- -
550 500 8
mA mA mA
2) 3)
ICC2 ICC3
-
- -
550 500
mA mA
2)
Semiconductor Group
565
HYM 322030S/GS-60/-70 2M x 32-Bit
DC Characteristics1) (cont'd) Parameter Average VCC supply current during fast page mode (RAS = VIL, CAS, address cycling, tPC = tPC min) -60 version -70 version Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -60 version -70 version Symbol Limit Values min. max. Unit Test Condition
ICC4
- -
550 500 4
mA mA mA
2) 3)
ICC5 ICC6
-
- -
600 550
mA mA
2)
Capacitance TA = 0 to 70 C, VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A11) Input capacitance (RAS0, RAS2) Input capacitance (CAS0 - CAS3) Input capacitance (WE) I/O capacitance (DQ0-DQ31) Symbol Limit Values min. max. 40 45 45 45 25 pF pF pF pF pF - - - - - Unit
CI1 CI2 CI3 CI4 CIO
Semiconductor Group
566
HYM 322030S/GS-60/-70 2M x 32-Bit
AC Characteristics 4) 5) TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values HYM 322030S/GS-60 min. Random read or write cycle time Fast page mode cycle time Access time from RAS Access time from CAS Access time from column address Access time from CAS precharge CAS to output in low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS pulse width (fast page mode) CAS precharge to RAS delay RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time CAS precharge time (fast page mode) Row address setup time Row address hold time Column address setup time Column address hold time
11) 6) 11) 12) 6) 11)
Unit
HYM 322030S/GS-70 min. 130 45 - - - - 0 0 3 50 70 70 40 20 70 20 20 15 5 10 0 10 0 15 max. - - 70 20 35 40 - 20 50 - 10000 200000 - - - 10000 50 35 - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
max. - - 60 15 30 35 - 20 50 - 10000 200000 - - - 10000 45 30 - - - - - -
tRC tPC tRAC tCAC tAA
110 40 - - - - 0 0 3 40 60 60 35 15 60 15 20 15 5 10 0 10 0 15
6) 12)
tCPA
6) 6) 7) 5)
tCLZ tOFF tT tRP tRAS tRASP tRHCP tRSH tCSH tCAS tRCD tRAD
12)
tCRP tCP tASR tRAH tASC tCAH
Semiconductor Group
567
HYM 322030S/GS-60/-70 2M x 32-Bit
AC Characteristics4) 5) (cont'd) TA = 0 to 70 C, VCC = 5 V 10 %, tT = 5 ns Parameter Symbol Limit Values HYM 322030S/GS-60 min. Column address to RAS lead time tRAL Read command setup time Read command hold time Read command hold time ref. to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Refresh period Write command setup time CAS setup time CAS hold time RAS to CAS precharge time CAS precharge time Write to RAS precharge time Write hold time ref. to RAS
13) 13) 10) 13) 13) 9) 9) 8)
Unit
HYM 322030S/GS-70 min. 35 0 0 0 15 15 20 20 0 15 - 0 10 10 5 10 10 10 max. - - - - - - - - - - 32 - - - - - - - ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns
max. - - - - - - - - - - 32 - - - - - - -
30 0 0 0 10 10 15 15 0 15 - 0 10 10 5 10 10 10
tRCS tRCH tRRH
8)
tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCP tWRP tWRH
Semiconductor Group
568
HYM 322030S/GS-60/-70 2M x 32-Bit
Notes
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) An initial pause of 200 s is required after power-up followed by 8 RAS cycles out of which at least one cycle has to be a refresh cycle before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (max) and VIL (max) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 6) Measured with a load equivalent of 2 TTL loads and 100 pF. 7) tOFF (max) defines the time at which the output achieves the open-circuit condition and is not referenced to output voltage levels. 8) Either tRCH or tRRH must be satisfied for a read cycle. 9) These parameters are referenced to the CAS leading edge. 10) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristic only. If tWCS > tWCS (min), the cycle is an early write cycle and data out pin will remain open (high impedance). 11) Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled by tCAS. 12) Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 13) For CAS-before-RAS cycles only.
Semiconductor Group
569

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